1. Field of the Invention
The present invention relates generally to solid state relays and more specifically to a photovoltaic solid state relay using a bidirectional switch.
2. Description of the Related Art
A photovoltaic solid state relay as disclosed in Japanese Patent No. 2, 522,249 includes a photovoltaic diode array and a bidirectional switch formed by a pair of MOSFETs series-connected across a pair of output terminals. The diode array responds to light from a light-emitting diode to generate a voltage corresponding to an electrical control signal supplied to the light-emitting diode. The voltage developed across the photovoltaic diode array is supplied through a discharging circuit to the transistors and applied across their gate electrodes and source electrodes so that the transistors are turned ON, establishing a current conducting path across a pair of output terminals to which an external load circuit is connected. For using the relay in an alternating current load circuit, the source-drain paths of the transistors are connected in opposite sense to each other. Since the impedance across the output terminals, which is desired to be as small as possible, equals the sum of on-resistances of the two transistors, a need exists to reduce the resistance across the output terminals. Furthermore, if the bidirectional switch is used for heavy load circuits, the source and gate electrodes must be connected to respective pads to provide the ability to carry high load current. However, the provision of such a pad structure requires a p-type well to be formed immediately below the pads. This structure would cause the capacitance of the relay to significantly increase, particularly when operating at high frequencies. Therefore, a need exists to reduce the capacitance of a bidirectional solid state relay for high frequency operation with a heavy load circuit.
It is therefore an object of the present invention to provide a photovoltaic solid state relay having a low output impedance.
Another object of the present invention is to provide a photovoltaic solid state relay having a low capacitance.
According to the present invention, there is provided a photovoltaic solid state relay having a pair of output terminals, comprising light emitting means for emitting light in response to an electrical control signal, first and second photovoltaic devices optically coupled to the light emitting means for converting the light to first and second voltages, respectively, and first and second unipolar transistors having first and second controlling electrodes for respectively receiving the first and second voltages and jointly establishing a first current conducting path between the output terminals. A bipolar transistor is provided having a base connected to a junction between the first and second unipolar transistors for establishing a second current conducting path in parallel to the first current conducting path between the output terminals in one of opposite directions depending on voltages applied to the output terminals.
In a preferred embodiment, the first and second unipolar transistors and the bipolar transistor are fabricated on a common semiconductor-on-insulator structure comprising a semiconductor substrate, a first insulator layer on the substrate, and a semiconductor layer on the first insulator layer. First and second backgate regions are formed in the semiconductor layer and first and second source regions are respectively formed in the first and second backgate regions. A common drain/base region is formed in the semiconductor region between the first and second backgate regions. A first insulated gate electrode is provided, bridging the first source region and the common drain/base region, and a second insulated gate electrode is provided, bridging the second source region and the common drain/base region. A second insulator layer is provided on the semiconductor layer. On the second semiconductor layer, first and second gate pads are formed and respectively connected to the first and second insulated gate electrodes to function as the first and second controlling electrodes of the unipolar transistors. On the second insulator layer, a first source pad is formed and connected to the first source region and the first backgate region and a second source pad is formed and connected to the second source region and the second backgate region, the first and second source pads being respectively connected to the output terminals. With this arrangement, the common drain/base region functions as a common drain of the first and second unipolar transistors and as the base of the bipolar transistor, and the first and second backgate regions respectively function as an emitter and a collector of the bipolar transistor when the first source pad is biased at a voltage higher than the second source pad, and respectively function as a collector and an emitter of the bipolar transistor when the second source pad is biased at a voltage higher than the first source pad.
For proper operation of the bipolar transistor, the first backgate region and the first source region are preferably in the shape of a first loop and the second backgate region and the second source region are in the shape of a second loop on the outer side of the first loop. The common drain/base region is in the shape of a loop between the first and second loops. The first insulated gate electrode is in the shape of a loop lying on the first loop and the second insulated gate electrode is in the shape of a loop lying on the second loop. The semiconductor layer is formed with first and second wells of conductivity type opposite to conductivity type of the semiconductor layer, the first well being surrounded by the common drain/base region and the common drain/base region being surrounded by the second well, the first and second wells penetrating through the semiconductor layer to the first insulator layer.